verilator/verilator

Digital logic design tool and simulator

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

Chisel: A Modern Hardware Design Language

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

A FPGA friendly 32 bit RISC-V CPU implementation

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

cocotb: Python-based chip (RTL) verification

GPGPU microprocessor architecture

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Scala based HDL